1. Field of the Invention
The present invention relates to a pipeline processing system and a microprocessor using the pipeline processing system, particularly to a pipeline processing system capable of executing each command having a plurality of memory operands respectively at high speed and its microprocessor.
2. Description of the Prior Art
In recent microprocessors, a so-called pipeline processing system is used in order to perform a high speed operation of each command. In the pipeline processing system, commands are divided into a plurality of stages and are executed by operating the stages in parallel, so as to improve the processing speed of the commands.
In these microprocessors in which commands are executed according to the pipeline system, in order to execute each of the commands having a plurality of memory operands in the microprocessors according to the prior art, effective addresses corresponding to each of the memory operands are calculated when each of the commands of the machine language is converted into a particular instruction style adapted to the pipeline processing.
For the purpose of calculating the effective addresses of the memory operands for a single command, the effective address corresponding to each memory operand was calculated independently by a plurality of effective address calculating circuits for calculating the effective address of the memory operand by providing the same number of the circuits as that of the memory operands in the microprocessors according to the prior art.
However, the provision of the plurality of effective address calculating circuits in the microprocessor resulted in a disadvantage that the microprocessor became excessively complex and it became large in size.
On the other hand, a method has also been proposed heretofore that the effective addresses corresponding to a plurality of memory operands are calculated successively one by one through a single effective address calculating circuit. According to this method, each of the effective addresses corresponding to the plurality of the memory operands can be calculated by the single effective address calculating circuit, as well. The calculation of the effective addresses, however, resulted in a problem that the execution time for the commands having a plurality of memory operands is delayed since the calculation had to be done successively for every one of the memory operands. Consequently, a high speed execution of the commands having a plurality of memory operands can not be performed in the latter case, as well.